1. Field
Exemplary embodiments of the present invention relate to a semiconductor, and more particularly, to a vertical channel transistor, a method for fabricating the same, and a semiconductor device including the same.
2. Description of the Related Art
Most semiconductor devices include transistors. For example, a memory cell of a memory device such as DRAM includes a cell transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET). In general, the MOSFET forms a source/drain area in a semiconductor substrate, and a planar channel is formed between the source area and the drain area. Such a MOSFET is referred to as a planar channel transistor.
Since the improvement of integration degree and performance of semiconductor devices has continuously improved, the fabrication technology of the MOSFET is approaching its physical limit. For example, with the decrease in size of memory cells, the size of the MOSFET has been reduced. Thus, the channel length of the MOSFET has also been inevitably reduced. When the channel length of the MOSFET is reduced, the characteristics of a memory device may be degraded due to various problems. For example, data maintenance characteristics may be degraded.
To overcome the above-described problem, a vertical channel transistor has been proposed. The vertical channel transistor has a source area and a drain area, which are formed in the upper and lower parts of a pillar. The pillar becomes a channel, and a vertical gate electrode is formed on sidewalls of the pillar.
FIG. 1 illustrates a conventional vertical channel transistor.
Referring to FIG. 1, the conventional vertical channel transistor includes a pillar P, a gate dielectric layer 13, and a gate electrode 14. The pillar P includes a source area 11B, a drain area 11A, and a vertical channel area 12.
The source area 11B and the drain area 11A may be formed in the upper and lower parts of the pillar P, respectively, through ion implantation, and may include an N-type junction area.
FIGS. 2A and 2B are energy band diagrams of the conventional vertical channel transistor.
Referring to FIG. 2A, with the size reduction of the silicon pillar, the vertical channel transistor is formed as a floating type so that a channel is isolated from a body by the N+ area. In such a structure, holes generated during transistor operation may not escape to the body but may accumulate in the channel as illustrated in FIG. 2B, thereby continuously increasing a channel potential.
As a result, a threshold voltage Vth may significantly vary, and junction leakage to the N+ area increases, thereby having negative effects on refresh characteristics, which are among the most important for DRAM.